Semiconductor device utiling an encapsulant for locking a semiconductor die to circuit substrate

ABSTRACT

An encapsulated integrated circuit is provided including a semiconductor die, a printed circuit board, and an encapsulant. The printed circuit board is conductively coupled to the semiconductor die and comprises a laminate defining first and second major faces. The laminate includes a solder resist layer, an electrically conductive layer, and a bismaleimide triazine resin laminate including a selected laminated layer and an adjacent laminated layer. The electrically conductive layer is interposed between the solder resist layer and the underlying substrate. The selected laminated layer is disposed closer to the first major face than the adjacent laminated layer. The laminate includes at least one void formed therein so as to extend from one of the major faces through the solder resist layer and the electrically conductive layer at least as far as the adjacent laminated layer. The void is characterized by a varying profile that defines a ledge portion in the selected laminated layer and an underlying cavity in the adjacent laminated layer. The encapsulant is positioned to mechanically couple the semiconductor die to the printed circuit board and to extend through the void into the underlying cavity so as to form an adhesive bond with the bismaleimide triazine resin laminate. The semiconductor die is supported by the bismaleimide triazine resin laminate and the encapsulant and the bismaleimide triazine resin laminate are arranged to enclose substantially all of the semiconductor die.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to semiconductor die encapsulationand, more particularly, to an encapsulation scheme that provides forimproved adhesion of the encapsulant to an underlying printed circuitboard.

[0002] Plastic encapsulates are commonly used in integrated circuitpackaging to protect the integrity of the encapsulated semiconductor dieand the associated electrical connections. U.S. Pat. No. 5,701,034(Marrs) is directed to providing improved encapsulation of asemiconductor die and teaches the formation of a locking moat in a heatsink to which the semiconductor die is coupled. The encapsulant materialis cured in the locking moat of the heat sink and about thesemiconductor die to interlock the encapsulant and the heat sink. Theteachings of U.S. Pat. No. 5,701,034 are not, however, related toimproving adhesion or coupling of the encapsulant to resin laminatescommonly utilized to form printed circuit boards. Further, the design ofthe locking moats and the structure of the heat sink in the '034 patentdo not complement each other to provide for an efficient method ofmanufacture.

[0003] In many instances, a semiconductor die is positioned on the uppersurface of a printed circuit board substrate and an encapsulant isarranged to cover the semiconductor die, portions of the upper surfaceof the substrate, and any leads, bond pads, or other bonding locationson the upper surface of the substrate. Robust encapsulant-to-substrateadhesion is critical in this type of structure because the encapsulantcontacts only the upper surface of the substrate, as opposed tocompletely surrounding the substrate and die.

[0004] In practice, encapsulant-to-substrate adhesion is limited byspecific design constraints. For example, the upper surface of thesubstrate typically includes conductive portions and solder resistportions. It is often difficult to identify a suitable encapsulant thatbonds equally well to the conductive portions and the solder resistportions. Further, the encapsulant material must also be selected tominimize the deleterious effects of particulate matter contaminating thesurface of the substrate. All of these design considerations limit theability to achieve sufficient encapsulant-to-substrate adhesion.

[0005] Accordingly, there is a need for a semiconductor dieencapsulation scheme that provides for optimum encapsulant-to-substrateadhesion while accounting for variations in the composition of thesubstrate surface and for the deleterious effects of particulate matteron the surface of the substrate, particularly where the substrateinvolved is a printed circuit board laminate. Further, there is a needin the art for an encapsulation scheme that is directed to improvingadhesion or coupling of the encapsulant to the resin laminates commonlyutilized to form printed circuit boards.

BRIEF SUMMARY OF THE INVENTION

[0006] This need is met by the present invention wherein a void isformed in the structure of a laminate supporting a semiconductor die andwhere an encapsulant is arranged to encapsulate the semiconductor dieand fill the void in the laminate.

[0007] In accordance with one embodiment of the present invention, apackaged semiconductor device is provided comprising a semiconductorchip, a laminate, and an encapsulant. The laminate defines first andsecond major faces and includes an electrically conductive layer, anunderlying substrate supporting the electrically conductive layer, andat least one void formed in the laminate so as to extend from one of themajor faces through the electrically conductive layer at least as far asthe underlying substrate. The encapsulant is positioned to mechanicallycouple the semiconductor die to the laminate to extend into the void soas to contact the underlying substrate.

[0008] The void or voids preferably extend into the underlying substrateand may extend from the first major face through the electricallyconductive layer and the underlying substrate to the second major face.The contact between the encapsulant and the underlying substrate ispreferably characterized by an adhesive bond and the encapsulantpreferably occupies substantially all of the void.

[0009] In accordance with another embodiment of the present invention, apackaged semiconductor device is provided comprising a semiconductorchip, a laminate, and an encapsulant. The laminate defines first andsecond major faces and includes a solder resist layer, an underlyingsubstrate, an electrically conductive layer interposed between thesolder resist layer and the underlying substrate, and at least one voidformed in the laminate so as to extend from one of the major facesthrough the solder resist layer and the electrically conductive layer atleast as far as the underlying substrate. The encapsulant is positionedto mechanically couple the semiconductor die to the laminate and toextend into the void so as to contact the underlying substrate.

[0010] In accordance with yet another embodiment of the presentinvention, a packaged semiconductor device is provided comprising asemiconductor chip, a laminate, and an encapsulant. The laminate definesfirst and second major faces and includes a plurality of laminatedlayers. The laminate also includes at least one void formed therein soas to extend from one of the major faces through a plurality of thelaminated layers. The encapsulant is positioned to mechanically couplethe semiconductor die to the laminate and is further positioned toextend into the void across the plurality of laminated layers so as tocontact a portion of the laminate between the first and second majorfaces of the laminate.

[0011] In accordance with yet another embodiment of the presentinvention, a packaged semiconductor device is provided comprising asemiconductor chip, a prepreg epoxy resin glass-cloth laminate, and anencapsulant. The prepreg epoxy resin glass-cloth laminate defines firstand second major faces and includes a plurality of laminated prepreglayers and at least one void formed therein so as to extend from one ofthe major faces through a plurality of the laminated prepreg layers. Theencapsulant is positioned to mechanically couple the semiconductor dieto the prepreg epoxy resin glass-cloth laminate and to extend into thevoid across the plurality of laminated prepreg layers so as to contact aportion of the laminate between the first and second major faces of thelaminate.

[0012] In accordance with yet another embodiment of the presentinvention, a packaged semiconductor device is provided comprising asemiconductor chip, a laminate, and an encapsulant. The laminate definesfirst and second major faces and includes a plurality of laminatedlayers and at least one void formed therein so as to extend from one ofthe major faces through a plurality of the laminated layers. The void ischaracterized by a profile that varies across adjacent laminated layers.The encapsulant is positioned to mechanically couple the semiconductordie to the laminate and to extend into the void across the varyingprofile so as to contact a portion of the laminate between the first andsecond major faces of the laminate. The varying profile may becharacterized by a cross-sectional area that changes from a first valuein a selected laminated layer to a second value in an adjacent laminatedlayer. The second value is preferably larger than the first value.

[0013] In accordance with yet another embodiment of the presentinvention, a packaged semiconductor device is provided comprising asemiconductor chip, a laminate, and an encapsulant. The laminate definesfirst and second major faces and includes a plurality of laminatedlayers, including a selected laminated layer and an adjacent laminatedlayer. The selected laminated layer is disposed closer to the firstmajor face than the adjacent laminated layer. The laminate includes atleast one void formed therein so as to extend from the first major facethrough the selected laminated layer and into the adjacent laminatedlayer. The void is characterized by a varying profile that defines aledge portion in the selected laminated layer and an underlying cavityin the adjacent laminated layer. An encapsulant is positioned tomechanically couple the semiconductor die to the laminate and to extendinto the void across the ledge portion into the underlying cavity so asto contact a portion of the laminate between the first and second majorfaces of the laminate. The selected laminated layer may comprise aplurality of laminated layers. Similarly, the adjacent laminated layermay comprise a plurality of laminated layers.

[0014] In accordance with yet another embodiment of the presentinvention, a packaged semiconductor device is provided comprising asemiconductor chip, a laminate, and an encapsulant. The laminate definesfirst and second major faces and includes a plurality of laminatedlayers and at least one void formed therein so as to extend from one ofthe major faces through a plurality of the laminated layers. The void ischaracterized by a cross-sectional area that changes from a first valuein a selected laminated layer to a second value in an adjacent laminatedlayer. The encapsulant is positioned to mechanically couple thesemiconductor die to the laminate, wherein the encapsulant is furtherpositioned to extend into the void across the varying cross-sectionalarea.

[0015] In accordance with yet another embodiment of the presentinvention, an encapsulated integrated circuit is provided comprising asemiconductor die, a printed circuit board, and an encapsulant. Theprinted circuit board is conductively coupled to the semiconductor dieand comprises a laminate defining first and second major faces. Thelaminate includes a solder resist layer, an underlying substrate, anelectrically conductive layer interposed between the solder resist layerand the underlying substrate, and at least one void formed in theprinted circuit board so as to extend from one of the major facesthrough the solder resist layer and the electrically conductive layer atleast as far as the underlying substrate. The encapsulant is positionedto mechanically couple the semiconductor die to the printed circuitboard and to extend into the void.

[0016] In accordance with yet another embodiment of the presentinvention, a computer is provided including at least one packagedsemiconductor device comprising a semiconductor chip, a laminate, and anencapsulant. The laminate defines first and second major faces andincludes an electrically conductive layer, an underlying substratesupporting the electrically conductive layer, and at least one voidformed in the laminate so as to extend from one of the major facesthrough the electrically conductive layer at least as far as theunderlying substrate. The encapsulant is positioned to mechanicallycouple the semiconductor die to the laminate and to extend into the voidso as to contact the underlying substrate.

[0017] In accordance with yet another embodiment of the presentinvention, an epoxy resin glass-cloth laminate is provided comprisingfirst and second major faces, and a plurality of laminated epoxy resinglass-cloth layers. The second major face is oriented substantiallyparallel to the first major face. The plurality of laminated epoxy resinglass-cloth layers define a portion of the laminate between the firstand second major faces. The laminate includes at least one void formedtherein so as to extend from one of the major faces through a pluralityof the laminated layers. The void is characterized by a profile thatvaries across adjacent laminated layers. The laminated layers preferablycomprise bismaleimide triazine resin.

[0018] In accordance with yet another embodiment of the presentinvention, an encapsulated integrated circuit is provided comprising asemiconductor die, a printed circuit board, and an encapsulant. Theprinted circuit board is conductively coupled to the semiconductor dieand comprises a laminate defining first and second major faces. Thelaminate includes a solder resist layer, an electrically conductivelayer, and a bismaleimide triazine resin laminate including a selectedlaminated layer and an adjacent laminated layer. The electricallyconductive layer is interposed between the solder resist layer and theunderlying substrate. The selected laminated layer is disposed closer tothe first major face than the adjacent laminated layer. The laminateincludes at least one void formed therein so as to extend from one ofthe major faces through the solder resist layer and the electricallyconductive layer at least as far as the adjacent laminated layer. Thevoid is characterized by a varying profile that defines a ledge portionin the selected laminated layer and an underlying cavity in the adjacentlaminated layer. The encapsulant is positioned to mechanically couplethe semiconductor die to the printed circuit board and to extend throughthe void into the underlying cavity so as to form an adhesive bond withthe bismaleimide triazine resin laminate. The semiconductor die issupported by the bismaleimide triazine resin laminate and theencapsulant and the bismaleimide triazine resin laminate are arranged toenclose substantially all of the semiconductor die.

[0019] In accordance with yet another embodiment of the presentinvention, a method of encapsulating an integrated circuit is providedcomprising the steps of (i) providing a semiconductor chip; (ii)providing a laminate defining first and second major faces, the laminateincluding an electrically conductive layer, and an underlying substratesupporting the electrically conductive layer; (iii) forming at least onevoid in the laminate so as to extend from one of the major faces throughthe electrically conductive layer at least as far as the underlyingsubstrate; and (iv) encapsulating the semiconductor die and the laminatewith an encapsulant such that the encapsulant extends into the void tocontact the underlying substrate.

[0020] In accordance with yet another embodiment of the presentinvention, a method of forming an epoxy resin glass-cloth laminate isprovided and comprises a process of laminating a plurality of epoxyresin glass-cloth layers such that the laminate includes at least onevoid formed therein extending from one of the major faces through aplurality of the laminated layers, and such that the void ischaracterized by a profile that varies across adjacent laminated layers.

[0021] Accordingly, it is an object of the present invention to providea packaged semiconductor device or encapsulated integrated circuit, acomputer including a packaged semiconductor device, a method ofencapsulating an integrated circuit, and a method of forming an epoxyresin glass-cloth laminate whereby an encapsulant may be arranged toencapsulate a semiconductor die and fill a void formed in the structureof a laminate supporting the semiconductor die. Other objects of thepresent invention will be apparent in light of the description of theinvention embodied herein.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0022] The following detailed description of the preferred embodimentsof the present invention can be best understood when read in conjunctionwith the following drawings, where like structure is indicated with likereference numerals and in which:

[0023]FIG. 1 is a schematic cross-sectional illustration of anencapsulated semiconductor die package according to the presentinvention;

[0024]FIG. 2 is a schematic, broken away, cross-sectional illustrationof a portion of a encapsulated semiconductor die package according toone embodiment of the present invention;

[0025]FIG. 3 is a schematic, broken away, cross-sectional illustrationof a portion of a encapsulated semiconductor die package according to analternative embodiment of the present invention; and

[0026]FIG. 4 is an exploded view of the encapsulated semiconductor diepackage illustrated in FIG. 3.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] Referring now to FIGS. 1 and 2, a packaged semiconductor deviceor encapsulated integrated circuit 10 according to the present inventioncomprises a semiconductor die or chip 20, a printed circuit boardlaminate 30 conductively coupled to the semiconductor die 20 (electricalconnections not shown), and an encapsulant 40.

[0028] The printed circuit board laminate 30 comprises a laminatedefining a first major face 31 and a second major face 32. At its firstmajor face 31, the laminate includes a solder resist layer 34, anelectrically conductive layer 36, and an underlying resin laminatesubstrate 38 supporting the electrically conductive layer 36 and thesolder resist layer 34. In the illustrated embodiment, the printedcircuit board laminate 30 includes an additional solder resist layer 34and an additional electrically conductive layer 36 at the second majorface 32 of the printed circuit board laminate 30.

[0029] The resin laminate 38 of the printed circuit board laminate 30 ispreferably a prepreg epoxy resin glass-cloth laminate, e.g., a BTlaminate (bismaleimide triazine), an FR-4 epoxy-glass laminate, an FR-5epoxy-glass laminate, or another suitable laminate structure. The resinlaminate 38 includes a plurality of adjacent laminated layers 38A-38F.The nature and extent of each laminated layer is perhaps bestillustrated in the exploded view illustration of FIG. 4.

[0030] A void 50 is formed in the printed circuit board laminate 30 andextends from the first major face 31, through the plurality of adjacentlaminated layers 38A-38F, to the second major face 32. The encapsulant40 is positioned to mechanically couple the semiconductor die 20 to theprinted circuit board laminate 30 by extending into the void 50 acrossthe plurality of laminated layers 38A-38F. The resulting contact betweenthe encapsulant 40 and the interior portion of the printed circuit boardlaminate 30 is characterized by an adhesive bond that solidifies thestructure of the encapsulated integrated circuit 10. Preferably, theencapsulant 40 occupies substantially all of the void 50. Further, theencapsulant 40 and the printed circuit board laminate 30 enclosesubstantially all of the semiconductor die 10.

[0031] Referring now to FIGS. 3 and 4, an alternative embodiment of thepresent invention is illustrated. In the embodiment of FIGS. 3 and 4,the void 50 is characterized by a profile that varies across theplurality of adjacent laminated layers 38A-38F. The encapsulant 40 (notshown in FIGS. 3 and 4) is arranged to extend into the void 50 acrossthe varying profile. In this manner, the varying profile functions tofurther secure the encapsulant within the void 50 and further solidifythe mechanical coupling between the semiconductor die 20 and the printedcircuit board laminate 30.

[0032] In the illustrated embodiment, the varying profile of the void 50defines a ledge portion 60 in the selected laminated layers 38A, 38B andan underlying cavity 62 in the adjacent laminated layer 38C such thatthe varying profile of the void 50 is characterized by a cross-sectionalarea that changes from a first value in the selected laminated layers38A, 38B to a larger value in the adjacent laminated layer 38C.Although, in the illustrated embodiment, two laminated layers 38A, 38Bdefine the ledge portion 60 and a single laminated layer 38C defines theunderlying cavity 62, it is contemplated by the present invention thatany number of layers may be selected to form the ledge portion 60 andthe underlying cavity 62. Further, although a simple T-shaped profile isillustrated in FIGS. 3 and 4, it is contemplated by the presentinvention that a variety of varying profiles may be utilized toaccomplish the objectives of the present invention.

[0033] As will be appreciated by those practicing the present inventionthe method of encapsulating the integrated circuit or semiconductor die20 comprises the steps of: (i) providing the semiconductor die 20; (ii)providing the printed circuit board laminate 30; (iii) forming the void50 in the laminate 30 such that it extends at least as far as theunderlying resin laminate substrate 38; and (iv) encapsulating thesemiconductor die 20 and the laminate 30 with an encapsulant 40 suchthat the encapsulant 40 extends into the void to contact the underlyingsubstrate 38. As will be further appreciated by those practicing thepresent invention, a variety of methods are available for forming thevoid 50. For example, the void 50 may be formed by drilling, stamping,or chemical etching. Further, it is contemplated by the presentinvention that the varying profile of the void 50 within the resinlaminate substrate 38 may be provided by processing separatelyindividual ones of the plurality of adjacent laminated layers 38A-38Fwith respective portions of the void 50 formed in selected ones of thelayers 38A-38F. Subsequently, the respective void portions of each layerare aligned to formed the desired profile and joined into a unifiedresin laminate substrate 38.

[0034] Having described the invention in detail and by reference topreferred embodiments thereof, it will be apparent that modificationsand variations are possible without departing from the scope of theinvention defined in the appended claims.

What is claimed is:
 1. A packaged semiconductor device comprising: asemiconductor chip; a laminate defining first and second major faces,said laminate including an electrically conductive layer, an underlyingsubstrate supporting said electrically conductive layer, and at leastone void formed in said laminate so as to extend from one of said majorfaces through said electrically conductive layer at least as far as saidunderlying substrate; and an encapsulant positioned to mechanicallycouple said semiconductor die to said laminate, wherein said encapsulantis further positioned to extend into said void so as to contact saidunderlying substrate.
 2. A packaged semiconductor device as claimed inclaim 1 wherein said at least one void extends into said underlyingsubstrate.
 3. A packaged semiconductor device as claimed in claim 1wherein said at least one void extends from said first major facethrough said electrically conductive layer and said underlying substrateto said second major face and wherein said encapsulant is positioned toextend through said void from said first major face to said second majorface.
 4. A packaged semiconductor device as claimed in claim 1 whereinsaid contact between said encapsulant and said underlying substrate ischaracterized by an adhesive bond.
 5. A packaged semiconductor device asclaimed in claim 1 wherein said encapsulant occupies substantially allof said void.
 6. A packaged semiconductor device as claimed in claim 1wherein said semiconductor chip is supported by said laminate andwherein said encapsulant and said laminate are arranged to enclosesubstantially all of said semiconductor chip.
 7. A packagedsemiconductor device comprising: a semiconductor chip; a laminatedefining first and second major faces, said laminate including a solderresist layer, an underlying substrate, an electrically conductive layerinterposed between said solder resist layer and said underlyingsubstrate, and at least one void formed in said laminate so as to extendfrom one of said major faces through said solder resist layer and saidelectrically conductive layer at least as far as said underlyingsubstrate; and an encapsulant positioned to mechanically couple saidsemiconductor die to said laminate, wherein said encapsulant is furtherpositioned to extend into said void so as to contact said underlyingsubstrate.
 8. A packaged semiconductor device comprising: asemiconductor chip; a laminate defining first and second major faces andincluding a plurality of laminated layers, said laminate including atleast one void formed therein so as to extend from one of said majorfaces through a plurality of said laminated layers; and an encapsulantpositioned to mechanically couple said semiconductor die to saidlaminate, wherein said encapsulant is further positioned to extend intosaid void across said plurality of laminated layers so as to contact aportion of said laminate between said first and second major faces ofsaid laminate.
 9. A packaged semiconductor device as claimed in claim 8wherein said at least one void extends from said first major facethrough said laminate to said second major face and wherein saidencapsulant is positioned to extend through said void from said firstmajor face to said second major face.
 10. A packaged semiconductordevice as claimed in claim 8 wherein said contact between saidencapsulant and said laminate is characterized by an adhesive bond. 11.A packaged semiconductor device as claimed in claim 8 wherein saidencapsulant occupies substantially all of said void.
 12. A packagedsemiconductor device as claimed in claim 8 wherein said semiconductorchip is supported by said laminate and wherein said encapsulant and saidlaminate are arranged to enclose substantially all of said semiconductorchip.
 13. A packaged semiconductor device comprising: a semiconductorchip; a prepreg epoxy resin glass-cloth laminate defining first andsecond major faces and including a plurality of laminated prepreglayers, said prepreg laminate including at least one void formed thereinso as to extend from one of said major faces through a plurality of saidlaminated prepreg layers; and an encapsulant positioned to mechanicallycouple said semiconductor die to said prepreg epoxy resin glass-clothlaminate, wherein said encapsulant is further positioned to extend intosaid void across said plurality of laminated prepreg layers so as tocontact a portion of said laminate between said first and second majorfaces of said laminate.
 14. A packaged semiconductor device comprising:a semiconductor chip; a laminate defining first and second major facesand including a plurality of laminated layers, said laminate includingat least one void formed therein so as to extend from one of said majorfaces through a plurality of said laminated layers, wherein said void ischaracterized by a profile that varies across adjacent laminated layers;and an encapsulant positioned to mechanically couple said semiconductordie to said laminate, wherein said encapsulant is further positioned toextend into said void across said varying profile so as to contact aportion of said laminate between said first and second major faces ofsaid laminate.
 15. A packaged semiconductor device as claimed in claim14 wherein said laminate includes a selected laminated layer and anadjacent laminated layer, said selected laminated layer is disposedcloser to said first major face than said adjacent laminated layer, saidvoid extends from said first major face through said selected laminatedlayer and into said adjacent laminated layer, and said varying profiledefines a ledge portion in said selected laminated layer and anunderlying cavity in said adjacent laminated layer.
 16. A packagedsemiconductor device as claimed in claim 14 wherein said varying profileis characterized by a cross-sectional area that changes from a firstvalue in a selected laminated layer to a second value in an adjacentlaminated layer.
 17. A packaged semiconductor device as claimed in claim16 wherein said second value is larger than said first value.
 18. Apackaged semiconductor device comprising: a semiconductor chip; alaminate defining first and second major faces and including a pluralityof laminated layers, including a selected laminated layer and anadjacent laminated layer, wherein said selected laminated layer isdisposed closer to said first major face than said adjacent laminatedlayer, said laminate includes at least one void formed therein so as toextend from said first major face through said selected laminated layerand into said adjacent laminated layer, and said void is characterizedby a varying profile that defines a ledge portion in said selectedlaminated layer and an underlying cavity in said adjacent laminatedlayer; and an encapsulant positioned to mechanically couple saidsemiconductor die to said laminate, wherein said encapsulant is furtherpositioned to extend into said void across said ledge portion into saidunderlying cavity so as to contact a portion of said laminate betweensaid first and second major faces of said laminate.
 19. A packagedsemiconductor device as claimed in claim 18 wherein said selectedlaminated layer comprises a plurality of laminated layers.
 20. Apackaged semiconductor device as claimed in claim 18 wherein saidadjacent laminated layer comprises a plurality of laminated layers. 21.A packaged semiconductor device comprising: a semiconductor chip; alaminate defining first and second major faces and including a pluralityof laminated layers, said laminate including at least one void formedtherein so as to extend from one of said major faces through a pluralityof said laminated layers, wherein said void is characterized by across-sectional area that changes from a first value in a selectedlaminated layer to a second value in an adjacent laminated layer; and anencapsulant positioned to mechanically couple said semiconductor die tosaid laminate, wherein said encapsulant is further positioned to extendinto said void across said varying cross-sectional area.
 22. Anencapsulated integrated circuit comprising: a semiconductor die; aprinted circuit board conductively coupled to said semiconductor die,wherein said printed circuit board comprises a laminate defining firstand second major faces, said laminate including a solder resist layer,an underlying substrate, an electrically conductive layer interposedbetween said solder resist layer and said underlying substrate, and atleast one void formed in said printed circuit board so as to extend fromone of said major faces through said solder resist layer and saidelectrically conductive layer at least as far as said underlyingsubstrate; and an encapsulant positioned to mechanically couple saidsemiconductor die to said printed circuit board, wherein saidencapsulant is further positioned to extend into said void.
 23. Acomputer including at least one packaged semiconductor devicecomprising: a semiconductor chip; a laminate defining first and secondmajor faces, said laminate including an electrically conductive layer,an underlying substrate supporting said electrically conductive layer,at least one void formed in said laminate so as to extend from one ofsaid major faces through said electrically conductive layer at least asfar as said underlying substrate; and an encapsulant positioned tomechanically couple said semiconductor die to said laminate, whereinsaid encapsulant is further positioned to extend into said void so as tocontact said underlying substrate.
 24. An epoxy resin glass-clothlaminate comprising: a first major face; a second major face orientedsubstantially parallel to said first major face; a plurality oflaminated epoxy resin glass-cloth layers defining a portion of saidlaminate between said first and second major faces, wherein saidlaminate includes at least one void formed therein so as to extend fromone of said major faces through a plurality of said laminated layers,and wherein said void is characterized by a profile that varies acrossadjacent laminated layers.
 25. An epoxy resin glass-cloth laminate asclaimed in claim 24 wherein said laminated layers include a selectedlaminated layer and an adjacent laminated layer, said selected laminatedlayer is disposed closer to said first major face than said adjacentlaminated layer, said void extends from said first major face throughsaid selected laminated layer and into said adjacent laminated layer,and said varying profile defines a ledge portion in said selectedlaminated layer and an underlying cavity in said adjacent laminatedlayer.
 26. An epoxy resin glass-cloth laminate as claimed in claim 24wherein said varying profile is characterized by a cross-sectional areathat changes from a first value in a selected laminated layer to asecond value in an adjacent laminated layer.
 27. An epoxy resinglass-cloth laminate as claimed in claim 26 wherein said second value islarger than said first value.
 28. An epoxy resin glass-cloth laminate asclaimed in claim 24 wherein said laminated layers comprise bismaleimidetriazine resin.
 29. An encapsulated integrated circuit comprising: asemiconductor die; a printed circuit board conductively coupled to saidsemiconductor die, wherein said printed circuit board comprises alaminate defining first and second major faces, said laminate includinga solder resist layer, a bismaleimide triazine resin laminate, includinga selected laminated layer and an adjacent laminated layer, and anelectrically conductive layer interposed between said solder resistlayer and said underlying substrate, wherein said selected laminatedlayer is disposed closer to said first major face than said adjacentlaminated layer, said laminate includes at least one void formed thereinso as to extend from one of said major faces through said solder resistlayer and said electrically conductive layer at least as far as saidadjacent laminated layer, and said void is characterized by a varyingprofile that defines a ledge portion in said selected laminated layerand an underlying cavity in said adjacent laminated layer; and anencapsulant positioned to mechanically couple said semiconductor die tosaid printed circuit board, wherein said encapsulant is furtherpositioned to extend through said void into said underlying cavity so asto form an adhesive bond with said bismaleimide triazine resin laminate,wherein said semiconductor die is supported by said bismaleimidetriazine resin laminate, and wherein said encapsulant and saidbismaleimide triazine resin laminate are arranged to enclosesubstantially all of said semiconductor die.
 30. A method ofencapsulating an integrated circuit comprising the steps of: providing asemiconductor chip; providing a laminate defining first and second majorfaces, said laminate including an electrically conductive layer, and anunderlying substrate supporting said electrically conductive layer;forming at least one void in said laminate so as to extend from one ofsaid major faces through said electrically conductive layer at least asfar as said underlying substrate; and encapsulating said semiconductordie and said laminate with an encapsulant such that said encapsulantextends into said void to contact said underlying substrate.
 31. Amethod of forming an epoxy resin glass-cloth laminate defining a firstmajor face and a second major face oriented substantially parallel tosaid first major face, said method comprising a process of laminating aplurality of epoxy resin glass-cloth layers such that said laminateincludes at least one void formed therein extending from one of saidmajor faces through a plurality of said laminated layers, and such thatsaid void is characterized by a profile that varies across adjacentlaminated layers.